(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming metal-to-silicon contacts.
(2) Description of prior art
The use of tungsten in the fabricating of very-large-scale integrated(VLSI) circuits has been in vogue since the mid 1980s. As a conductive material tungsten does not rank as high as aluminum, which has been the primary conductor used in micro-circuit chip technology for nearly forty years. On the other hand, tungsten provides many features which make it an important material for fabricating metal-to-silicon contacts. In this capacity tungsten is deposited into contact openings, vertically etched into an insulating layer covering the silicon. These contact openings expose active areas of the subjacent semiconductor devices. The tungsten plugs are then connected to aluminum alloy conductors at the upper surface of the insulating layer. The short length of conductive path thus provided by the tungsten plug has no significant impact on the conductivity of the overall interconnect line.
Chemical vapor deposited(CVD) tungsten has proven to be an excellent material for such interconnect applications because of its low resistance, low stress(less than 5.times.10.sup.9 dynes/cm.sup.2), and a coefficient of thermal expansion which closely matches that of silicon. In addition tungsten has a high resistance to electromigration which is a common problem with aluminum its alloys. CVD tungsten can be deposited at temperatures around 400.degree. C. with good conformity and step coverage.
Although tungsten does not bond well to either silicon or the adjacent silica based insulating layer, a thin layer(less than 1,000 Angstroms) of titanium(Ti) is often used as a bonding agent to the silicon. Dixit et.al. U.S. Pat. No. 4,960,732 describe the formation of a tungsten plug contact utilizing Ti as a bonding agent followed by a layer of titanium nitride(TiN) which acts as a diffusion barrier to prevent dopants from passing from the silicon as well as spiking of metal into the Silicon. The Ti layer, when thermally annealed fuses with the silicon to form titanium silicide(TiSi.sub.2) and with the silica based insulating layer to form a titanium silicate(Ti.sub.x SiO.sub.y). Adhesion of the TiN to the Ti and subsequently the tungsten to the TiN is considered excellent.
The Ti--TiN--W composite tungsten plug metallurgy has been widely accepted and various techniques for its formation have been described. In the earliest teachings such as those of Dixit et.al., the Ti an TiN layers were deposited by sputtering although CVD is also claimed. The sputtering can be accomplished by first sputtering a titanium target with argon to form the Ti layer and then admitting nitrogen, thereby sputtering reactively, to form the TiN layer. Alternatively, a multi-target sputtering tool can be used having a Ti target and a TiN target so that the layers may be deposited during a single evacuation cycle by switching targets within the tool. Successive deposition of the Ti and the TiN layers during a single pumpdown is important because exposure of the Ti layer to atmosphere will immediately result in the formation of a native oxide layer which can compromise the resistivity of the contact if not removed prior to the deposition of the TiN.
The good conformity and step coverage afforded by tungsten is due in large part to the nature of the deposition process itself. In the CVD process, particularly with low pressure chemical vapor deposition(LPCVD), the chemical reaction which forms the product occurs at the heated surface of the material receiving the deposition. Physical vapor deposition(PVD) processes such as evaporation or sputtering, cannot provide such good conformity and edge coverage because the material being deposited arrives from regions distant from its final location. This lends directionality to the process and consequently those regions of a receiving substrate which face the source of the particle stream receive the greater amount of deposit than those topological features not normal to the particle stream. Step coverage can be improved to some extent by heating of the substrate wafer. This allows some degree of surface migration of the depositing species to occur, thereby improving conformity.
Consequently the sputtering processes for the deposition of Ti and TiN have the shortcoming of poor step coverage. This is illustrated in a prior art cross section shown in FIG. 1A. A semiconductor wafer 6, having an active area diffusion 8 has an insulating layer 10 into which a contact opening has been made and a thin layer of Ti 12 followed by a thicker layer of TiN 14 have been deposited by sputtering. Inadequate step coverage causes the negatively tapered overhang of TiN 16. The subsequently deposited tungsten layer then prematurely pinches off before the bottom of the opening is filled. The result is a void 20 shown in FIG. 1B. When the tungsten layer is etched back to the insulating layer 10(FIG. 1C) or to the TiN layer 14, the void 20 is exposed creating a potential reliability defect.
Chen U.S. Pat. No. 5,462,895 also points out this step coverage shortcoming but does not indicate the occurrence of voids in the tungsten. However, such voids have been observed by scanning electron microscopy(SEM). Further, the occurrence of exposure of these voids after tungsten etchback can be clearly seen by SEM (See FIG.3A). At this point they are highly susceptible to absorption of moisture or other corrosive contaminants.
Chen resolved the edge coverage problem by using CVD for the deposition of the Ti and TiN layers, thereby achieving better conformity. However, because of thermal budget restraints and other processing impediments, CVD is not always a viable option. In addition, even CVD step coverage is inadequate to avert voids where high aspect ratio openings are encountered.
Nagashima U.S. Pat. No. 5,312,773 forms a tungsten plug as an interlevel connection structure. However, he covers a TiN layer along the walls with a silicon oxide layer and utilizes selective tungsten deposition whereby the tungsten does not deposit on the silicon oxide wall but grows upward from the bottom of the opening. The base of the opening is not a device active area but a polysilicon layer which has no Ti or TiN over it.